SPE is a schematic capture package developed by Gärtner Electronic Design GmbH for entering the schematics of integrated electronic circuits with flexible assignment of net names, pinnames and instance names.  Storage of schematic and symbol data as ASCII-text.

The program is an application for Windows 95 /98/ME/2000/NT and runs on personal computers AT/486 and above. 

• Schematic graphical data may be created and processed in hierarchical structured forms. 
• Input file can be an ECS-Synario /Cohesion HDS ASCII file.
• No limit to the number of hierarchical level for a schematic.
• Allows movement up and down in the hierarchy.
• Data comprises of symbols, schematic elements, attributes, text, buses, bus taps, pins and wires (nets connecting the used components.
• Symbols are the basic elements of a schematic and represent primitive devices, resistors, gates, etc. or complex sub-circuit "BLOCK" symbols.
• Attributes describe characteristics or properties of associated symbols, pins or nets.
• Symbol files are contained in library directions used for several schematics.
• SPE stores the schematic in ASCII format, which can be converted to and from a number of standard formats.
• SPE includes NETLISTER for the output of net list files and formats as XNDL, PSpice, HSpice) layout generation (place/route tools like Catena's LAYPAR) and for layout verification, e.g. CATENA's LAYVER.
• Cross probing can be carried out together with the LAYVER evaluation tool LAYED.
• Schematic consistency checks can be carried out.
• Back annotations for simulation results currently supported by Dolphin Integration's SMASH.
• The input file may be an ECS-Synario™ ASCII file.
• Easy navigation within the hierarchy levels 
• Creation of own symbols 
• Definition of attributes for symbols, symbol
  instances and pins  
• Use of symbol libraries 
• Flexible assignment of net names, pinnames
  and instance names 
• Storage of schematic and symbol data as ASCII-text 
• Creation of net lists for circuit simulation
  with (SPICE, VHDL, HILO, SMASH), for
  layout generation (LAYPLACE/LAYROUTE),
  for layout verification (LAYVER) or output
  as EDIF2 or SDL-netlist 
• Cross probing between circuit and layout
  (SPE<->LAYVER) 
• SMASH back annotation 
• Consistency checks 
• Creates and processes schematic graphical data in a hierarchical structured form 
• Unlimited to the number of hierarchical level for a schematic.
• Free navigation in hierarchy from the schematic view is possible. 
• Supports the following data elements: symbols, schematic elements, attributes, text, buses, bus taps, pins, and wires (nets) 
• Free customization of symbols is possible, both primitive devices (such as
  transistors, resistors, and gates) and complex sub-circuits referred to as "block" symbols 
• Uses attributes to describe the characteristics or properties of symbols and pins 
• Supports the establishment of reference directories for symbol files 
  Flexible naming of instances, nets, and buses is possible. 
• Uses an open ASCII format for schematic files so that data can be converted to and from a number of standard formats 
• SPE-Netlister generates net lists that may be used directly for simulation (for example, using PSpice or HSpice), for automatic layout generation (using Place & Route such as LAYPAR from Catena Software GmbH), or for layout verification (for example, using LAYVER also from Catena) 
• Can be used to cross-probe between schematic and layout implementation using the LAYVER evaluation tool LAYED. 
• SPE checks the schematic consistency (connectivity checking) 
• Back annotation for simulation results is possible (SMASH results). 
  

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