LAYVER is a sophisticated layout verification package. It offers design rule checking, circuit extraction, parameter extraction, and layout against net-list comparison functions all under one package.   Data output may be evaluated using an extension  to the LAYED package.

It operates on Windows,  OS/2, and Windows NT, LINUX, and UNIX. 

layver_crossprobing.gif (59076 bytes)

  • Database conversion (for example reads GDSII)
  • Comprehensive layer operations (selection, logical, sizing)
  • Operations on polygons, edges, or text
  • Includes check filters (for example parallel, nodal
  • Full flexibility of circuit extraction using user-defined devices
  • Net-list to net-list comparison option
  • User-defined expressions for parameter extraction
  • Outputs net-list in standard formats (for example HSpice)
  • Net-list to net-list comparison option
  • Comprehensive evaluation of output data using additional LAYED modules to provide  
    •   graphical and textual DRC error identification
    •   graphical identification of nodes, devices, generated layers,   shorts, etc.
  • Access to all layers generated
  • Schematic to layout cross-probing including SPE.

 




Stand-alone verification tool with layer operations, DRC, extract, LVS and conversion utilities (DBX, GDSII, DXF).


Stand-alone verification tool with layer operations, DRC and conversion utilities (DBX, GDSII, DXF); without extract and LVS.


Stand-alone tool with layer operations and conversion utilities (DBX, GDSII, DXF); without DRC, extract, and LVS.

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